Since 2009, the mobile industry has experienced an unprecedented number of new trends. The current trend sees gadgets providing low-power mobility without compromising performance.
When users realized the advantages of browsing the web, watching HD video, and playing 3D games on a mobile device, they demanded displays with higher resolution and better multimedia performance.
Designed to keep up with these mega trends, Exynos 5 Dual supports a WQXGA solution.
Exynos 5 Dual key features:
System-on-a-chip (SoC) based on the 32-bit RISC processor for tablet PCs. Designed with the 32nm lowpower process, Exynos 5 Dual provides performance features such as dual core CPU, highest memory bandwidth, WQXGA display, 1080p 60fps video hardware, 3D graphics hardware, Image Signal Processor, and high-speed interfaces such as USB 3.0 and SATA3.
Cortex-A15 dual core (with each core running at 1.7GHz speed), whose DMIPS is 40% higher than Cortex-A9 core.
12.8GB/s memory bandwidth with 2-port 800MHz LPDDR3 for heavy traffic operations such as 1080p video en/decoding, 3D graphics display, and high-resolution image signal processing with WQXGA display. Exynos 5 Dual supports dynamic virtual address mapping, which helps software engineers fully utilize memory resources.
The best 3D graphics performance with a variety of APIs, such as openGL ES 2.0 and Halti, that can be used for GPUs with openCL full profile.
1080p 60fps video performance, which is critical for 3D stereoscopic playback/record and wireless display.
WQXGA resolution of display subsystem, making it different from its competitors. For the first time in the mobile industry, Exynos 5 Dual integrates eDP controller and PHY transceiver to save power, space and bill of materials (BOM). Integrated eDP is specially designed with low-power circuit and features hardwired logic to support Panel-Self-Refresh (PSR) protocol.
Image Signal Processor (ISP) of 8M pixel 30fps with addon post processing units, such as 3-Dimensional Noise Reduction (3DNR), Vdeo Dgital Image Stabilization (VDIS), and Optical Distortion Compensation (ODC) integrated. Its ISP pipeline supports zero-shutter lag.
BOM savings by integrating USB Host/Dev3.0, HSIC with PHY transceivers, and eight channels of I2C supporting a variety of sensors.