Quoting from ECMA-130, Annex B:
A regular bit pattern fed into the EFM encoder can cause large values of the digital sum value in case the merging bits cannot reduce this value
i don’t think it’s that simple though. you forget about the circ coding between scrambling and efm.
I’ll check for this soon, I’ve got to leave for church now, however, the CIRC only accounts for 8 bytes, and I can’t find exactly how it is interleaved, or just added at the end, or put in the P and Q subchannels (as hinted by the naming of the Parity bytes P and Q). My guess is the subchannels.
I mean Annex B, not Annex E. Annex E describes the merging bits themselves.