Unfortunately it's down to physics. If you shrink the NAND you also shrink the write cycles.
You can get around this but the cost is prohibitive.
As a rough guide for MLC NAND
50nm = 10,000 cycles
34nm = 5,000 cycles
25nm = 3,000 cycles, but could be as low as 1,500 cycles
Another way, and the one that SandForce uses, are new ways of bringing down write amplification. SandForce uses a technology they call DuraClass, which compresses data before it's written to NAND, and also employs very smart garbage collection algorithms.
I don't think Intel will use compression, but let's wait and see.