I have sorted it out correctly now by reading a lot:
On the Nehalem architecture the main clock generator was on the motherboard which is traditional design. It was always there. For Nehalem it was a 133MHz generator.
PCI-E and SATA had one or two seperate 100MHz generators which I don’t know where they reside.
The Sandy Bridge platform has an integrated 100MHz generator. Having a choice of putting it into the CPU or the PCH, intel chose to put it into the PCH. socket 2011 + The Sandy Bridge E + X68 PCH platform will put the clock generator back to the motherboard.
And the restriction of modifying the clock does not have anything to do with the position of the generator of course. The problem is that intel created a unified generator from main CPU clocks down to USB clock. PCI-E, SATA and USB fail after increasing just a few MHz base clock. If there’s a hard restriction besides that I don’t know.
With the external generator for the X68 PCH an access to different multipliers will be possible again from BIOS.
I was also able to understand full Sandy Bridge internals. But this is a lot and I had a huge headache after having read for days about it. The parts that are relevant for end-consumers is very little and simple facts. It’s just tons of false info and tons of true but pro facts you have to go through before you can seperate that little form the huge masses. The ring bus and those things are really interesting design. So it was worth the work.
Z68 PCH: This is nothing official yet afaik. What I said above was in previous post was in the thought that it’s official. On that “leaked” card it says socker 1155. If Z68 is not a rumor, it’s indeed a third chipset. A special chipset with external generator for the 1155 Sandy Bridges.